As semi-conductor devices are becoming smaller and smaller, system on chip devices are being produced with more and more different processing elements integrated on the same chip.
These processing elements previously have been provided as separate semi-conductor devices.
The semi-conductor devices perform their functions in response to clock signals which are provided at one or more inputs to the device, and are divided and distributed internally to the various processing elements. Where different processing elements form part of the same system and signals are transferred between them, a common clock is normally used. If the various processing elements have different clock frequency requirements then some consideration needs to be given to how data is transferred between those modules. Data transfer can be kept simple if the modules are clocked at integer clock ratios with respect to each other. It is seen, however, that if arbitrary clock ratios are required then more expensive and complex synchronisation is required, and this can result in an increased latency penalty on data transfers.
A typical example SoC device is shown in FIG. 1. This comprises a plurality of modules 2, 4 and 6. These modules 2, 4 and 6 may be any combination of central processing units, co-processors, interfaces, arbitration units, or any other circuitry required by the SoC that is driven by a clock.
A master clock signal 8 is provided to phase lock loop (PLL) 10. Module 1 takes the clock signal from the PLL 10 as clock 1 and performs its functions at this clocking rate.
Modules 2 and 3 do not need to run as fast as the frequency of clock 1 which is provided to module 1. Therefore, the clock signal to module 2 (clock 2) passes through a divide by N unit 12 and the clock input to module 3 (clock 3) passes through a divide by M unit. In this case, N and M are integer amounts. Clocking modules 2 and 3 at a lower rate minimises power consumption by these modules.
It will be appreciated that provided M and N are kept at simple integer ratios and all three clocks are carefully synchronised, the transfer of the data between the modules may be kept relatively simple. For example, it can be arranged that module 1 will only update its outputs to and read its inputs from module 2 every N clock cycles. Similarly, module 1 will only transfer the data to and read its inputs from module 3 once every M clock cycles.
If other ratios of M and N are used (i.e. non integer values) the transfer of the data between the modules can become more complex and it can become necessary to insert a first in first out (FIFO) buffer or some special synchronisation logic 16 as shown between modules 2 and 3 in FIG. 1.
Some processing systems will have processing requirements which are dynamically variable. Thus, a circuit such as FIG. 1 could use module 1 to perform a significant amount of processing before module 2 performs any processing at all. If module 2 were clocked at the same rate as module 1 then there would be unnecessary power consumption by module 2 in the first stage of the process. If module 2 is operated at a lower clock frequency then the second part of the process would be performed more slowly than the first part. Dynamic variation of clock speed is desirable to provide optimal processing rates in such situations but difficult to achieve, especially when there is a requirement to transfer the data between the modules running at different clock frequencies.